Memory switches are commonly used in small to medium size devices. Ingress data units such as packets that arrive at the memory switch are classified, placed in queues in the memory, and eventually scheduled to be transmitted from their destination port. In many cases ingress data units are also processed by applying various manipulations such as editing packet headers, adding headers, removing headers and the like.
On-chip memory is typically too small to store large sized packet queues and thus off chip memory (usually DDR) is used to store the data queues.
Managing the off-chip memory is a complex task due to the high rate of incoming and outgoing packets, and the need to manage a large number of queues. As a result, memory switch architectures are built around a single frame structure. If incoming or outgoing data is formatted according to another format then the memory switch has to convert this other format to the single frame structure. For example, an Ethernet switch can have an ATM interface through which Ethernet frames arrive fragmented into cells; the cells are reassembled to an Ethernet frame at the input port on the chip or through additional external memory access before been stored in the adequate queue. This translation hardware (the reassembly hardware in the example above) requires a large memory, increases the chip costs, and reduced the operation rate or the number of supported ports or queues.
In addition, prior art devices used to perform multiple memory accesses in order to perform protocol interworking and processing and then send the processed data units to queues. Using smaller queues can increase the memory allocation efficiency but on the other hand using a large number of buffers requires a large number of pointers to these buffers. Free buffers are pointed by free buffers. The management of large number of free buffer pointer further complicates memory management and storing a free buffer list at a dedicated storage unit further increases the cost of memory management.
In addition, various memory unit management, such as DDR memory management, is characterized by low utilization.
There is a growing need to provide efficient devices and method for storing and processing high bandwidth, high capacity, multi queues data packets.